This paper proposes a novel Vision Transformer (ViT)-based data augmentation framework for wafer map defect classification, aiming to enhance the resilience of semiconductor supply chains.

Table 20. Summary of experimental results using different strategies.

Technology Overview
The core of this research is a new data augmentation framework that uses Vision Transformer (ViT) models. The main goal is to solve the problem of imbalanced image data categories in semiconductor manufacturing, where some types of wafer defects are very rare. The ViT model generates new, synthetic wafer map defect images, especially for these minority classes. This is achieved by analyzing the ViT's internal mechanisms, specifically its modified Multi-Head Self-Attention (MSA) and Multi-Layer Perceptron (MLP). The research innovatively uses the multi-head outputs of ViT to create heatmaps for data augmentation. This approach is compared to a benchmark model, CycleGAN, demonstrating its superior effectiveness in boosting classification accuracy for individual minority classes.

Applications & Benefits
This technology significantly contributes to sustainable development in semiconductor manufacturing. By improving the accuracy of wafer map defect classification, it helps reduce waste, enhance resource efficiency, and improve overall quality control. This directly supports sustainable manufacturing principles and eco-friendly production practices. The ability to better classify defects leads to higher manufacturing yields for both front-end-of-line (FEOL) and back-end-of-line (BEOL) processes. By understanding defect patterns and their correlation with process parameters, manufacturers can implement proactive measures to improve product quality, minimize resource consumption, and reduce waste.

Abstract：
Wafer map defect classification plays a crucial role in sustaining the semiconductor supply chain during industrial disruptions by ensuring continuity, resilience, and efficiency while aligning with sustainability principles. Up to 30 percent of production costs is lost to chip testing and yield losses for semiconductor manufacturing supply chain. In the semiconductor practice, wafer map defects recognition plays a linchpin role in the front-end-of-line stage. Defect pattern recognition can directly pinpoint the assignable causes and provide the domain experts with actionable insights. However, various wafer defect types occur differently from each other, which makes the collected wafer map dataset to be highly imbalanced in defect classes. In the face of data imbalance, the classification model usually cannot provide satisfactory classification performance. In this aspect, this paper intends to investigate the wafer defect map classification problem by using Vision Transformer (ViT) as an alternative data augmentation approach. The primary purpose is to alleviate the class-imbalance issue and then the performance of a deep learning-based convolutional neural network for wafer defect classification can be effectively improved. The experimental results demonstrate that the proposed data augmentation method by using ViT proves to be a potential generative model for improving wafer map defect classification, particularly robust on the individual minority class. In a word, the proposed augmentation framework for wafer map defect classification facilitates a more targeted and efficient approach to quality control, resource utilization, and production optimization in maintaining a sustainable semiconductor supply chain, particularly in times of industrial disruption.

A new ViT-Based augmentation framework for wafer map defect classification to enhance the resilience of semiconductor supply chains
Author：Shu-Kai S. Fan, Shang-Hao Chiu
Year：2024
Source publication：International Journal of Production Economics Volume 273, July 2024
Subfield Highest percentage：99%  General Business, Management and Accounting  #2 / 225

https://www.sciencedirect.com/science/article/pii/S0925527324001324